1. Field
Example embodiments relate to a wafer burn-in test, for example, a method and a semiconductor device for generating a test voltage for a wafer burn-in test.
2. Description of the Related Art
In general, a screening test may be performed at an early stage to identify if a semiconductor memory device, for example, dynamic random-access memory (DRAM), has any defects; the screening test may include a wafer burn-in test. The wafer burn-in test may identify potential defects in the semiconductor memory device by exposing the semiconductor memory device to worst-case scenario conditions, for example, a high temperature and a high voltage, for a short time period. The wafer burn-in test may be performed to detect the defects in the semiconductor memory device at an early stage, before a semiconductor wafer is divided into a plurality of memory chips.
During the wafer burn-in test, an appropriate voltage may be applied to the wafer to detect the defects in the semiconductor memory device.
Generally, a driving voltage for the wafer burn-in test may be supplied from a wafer burn-in test device, where the driving voltage may include a DRAM logic control driving voltage (VDD), a word-line voltage (VPP), and a bit-line voltage (VBL).
FIG. 1 is a block diagram illustrating a conventional procedure that may provide a bit-line voltage (VBL) to a memory cell array when a wafer burn-in test is not being performed.
A bit-line voltage driving circuit 110 may be a circuit applying the bit-line voltage to the memory cell array when the wafer burn-in test is not being performed. For example, the bit-line voltage driving circuit 110 may provide the bit-line voltage to the memory cell when the wafer burn-in test is not being performed. The operation of the bit-line voltage driving circuit 110 is described later.
A bit-line voltage pad 120 may be a voltage pad to which the bit-line voltage may be applied from the wafer burn-in test device when the wafer burn-in test is being performed, and may be floated when the wafer burn-in test is not being performed. For example, when the bit-line voltage is high, a value of “1” may be written into the memory cell, and when the bit-line voltage is low, a value of “0” may be written into the memory cell.
Thus, when the wafer burn-in test is not being performed, the bit-line voltage pad 120 may not generate the bit-line voltage, but the bit-line voltage driving circuit 110 may generate the bit-line voltage.
FIG. 2 is a conventional circuit diagram illustrating the bit-line voltage driving circuit in FIG. 1.
Referring to FIG. 2, the bit-line voltage driving circuit 110 may include a reference voltage generator 210, a first comparator 220, a second comparator 230, a pull-up transistor 240 and a pull-down transistor 250.
The reference voltage generator 210 may receive a voltage from a power supply voltage VDD to generate first and second reference voltages. For example, the first reference voltage may be lower than the bit-line voltage and the second reference voltage may be higher than the bit-line voltage.
The first comparator 220 may compare a voltage VBL of the bit-line voltage driving circuit 110 with the first reference voltage to output a first comparison signal. For example, the first comparison signal may correspond to a logic “high” when the voltage VBL of the bit-line voltage driving circuit 110 is higher than the first reference voltage, and the first comparison signal may correspond to a logic “low” when the voltage VBL of the bit-line voltage driving circuit 110 is lower than the first reference voltage.
The second comparator 230 may compare the voltage VBL of the bit-line voltage driving circuit 110 with the second reference voltage to output a second comparison signal. For example, the second comparison signal may correspond to a logic “high” when the voltage VBL of the bit-line voltage driving circuit 110 is higher than the second reference voltage, and the second comparison signal may correspond to a logic “low” when the voltage VBL of the bit-line voltage driving circuit 110 is lower than the second reference voltage.
The pull-up transistor 240 may pull up the voltage VBL of the bit-line voltage driving circuit 110 based on the first comparison signal. For example, the pull-up transistor 240 may be implemented with a p-type metal-oxide semiconductor (PMOS), where the pull-up transistor 240 may pull up the voltage VBL of the bit-line voltage driving circuit 110 when the first comparison signal that may be applied to a gate of the PMOS is a logic “low.”
The pull-down transistor 250 may pull down the voltage VBL of the bit-line voltage driving circuit 110 based on the second comparison signal. For example, the pull-down transistor 250 may be implemented with an n-type MOS (NMOS), where the pull-down transistor 250 may pull down the voltage VBL of the bit-line voltage driving circuit 110 when the second comparison signal that may be applied to a gate of the NMOS is a logic “high.”
When the output voltage VBL of the bit-line voltage driving circuit 110 is lower than the first reference voltage, the first comparator 220 may generate the first comparison signal of a logic “low” and the pull-up transistor 240 may pull up the voltage VBL of the bit-line voltage driving circuit 110.
When the output voltage VBL of the bit-line voltage driving circuit 110 is higher than the second reference voltage, the second comparator 230 may generate the second comparison signal of a logic “high” and the pull-down transistor 250 may pull down the voltage VBL of the bit-line voltage driving circuit 110.
When the output voltage VBL of the bit-line voltage driving circuit 110 is higher than the first reference voltage and lower than the second reference voltage, the first comparator 220 may generate the first comparison signal of a logic “high” and the second comparator 230 may generate the second comparison signal of a logic “low.”
Therefore, the output voltage VBL of the bit-line voltage driving circuit 110 may correspond to about VDD/2 and may be maintained between the first reference voltage and the second reference voltage.
FIG. 3 is a block diagram illustrating a conventional procedure for providing a bit-line voltage (VBL) to a memory cell array, when the wafer burn-in test is being performed.
The bit-line voltage driving circuit 110 may not operate when the wafer burn-in test is being performed. The reason is that the wafer burn-in test device may provide, to the memory cell array, a voltage that may be higher than that of the bit-line voltage driving circuit 110 when the wafer burn-in test is not being performed.
A bit-line voltage pad 120 may be a voltage pad to which the bit-line voltage is applied from the wafer burn-in test device when the wafer burn-in test is being performed, and may be floated when the wafer burn-in test is not being performed. For example, when the bit-line voltage is high, a value of “1” may be written into the memory cell, and when the bit-line voltage is low, a value of “0” may be written into the memory cell.
The wafer burn-in test device may provide the bit-line voltage pad 120 with a higher voltage when the wafer burn-in test is being performed than when the wafer burn-in test is not being performed. A higher current may thus be applied to the memory cell array when the wafer burn-in test is being performed than when the wafer burn-in test is not being performed.
Accordingly, as the capacity of a semiconductor memory device is increased, the bit-line voltage for the wafer burn-in test may also be increased, and thus the bit-line voltage that may be provided from the wafer burn-in test device may be reduced. For example, a sufficient voltage that may be used in the wafer burn-in test may not be provided from the wafer burn-in test device, because of a limitation in the wafer burn-in test device.